1. Field of the Invention
The present invention relates to a stacking type semiconductor chip package and, more particularly, to a stacking type semiconductor chip package of a LOC (Lead On Chip) structure which is modified for stacking chips in the package.
2. Discussion of the Conventional Art
In general, a LOC package, which represents a large scale integration technique, has an end of a lead frame lead to the central top portion of a chip where it is connected by wire bonding to a pad, which functions as an external terminal on the central part of the chip. In comparison to prior type packages, such as DIP which has lead frames arranged on the sides of chips, the LOC package is advantageous in that the width of a chip placed within the width of a molding body can be made wider.
FIG. 1 illustrates an example of a conventional LOC package disclosed by U.S. Pat. No. 5,068,712. In fabricating the conventional LOC package of U.S. Pat. No. 5,068,712, a semiconductor chip 5, having a center pad 4 provided in the central part of the package and an insulating coating on top of the chip is attached to an inner lead 1a of a lead 3a using a double-faced adhesive insulating tape 8a. Then, a wire bonding is conducted in which the inner lead 1a of the lead frame and the center pad 4 are connected with a wire 9 having a very fine metallic line. The package is molded with a molding resin 10 to complete the packaging.
However, the conventional package has the following disadvantage.
The conventional LOC package, which contains only one chip within the molding body 10, is not effective in increasing the capacity of its semiconductor chip package. If it is intended to increase the integration capacity of the semiconductor chip package by mounting many packages on a mounting board, this approach is not advantageous toward making an electronic device lighter, thinner, shorter, and smaller because the mounting board will become too large.